1. Field of the Invention
The present invention relates to a cell construction of a semiconductor memory device, and in particular to an improved method for controlling the semiconductor memory device capable of extending a refresh interval by lengthening a storing time of a cell data in a cell capacitor.
2. Description of the Conventional Art
FIG. 1 is a diagram illustrating the construction of a conventional memory device. As shown therein, the conventional memory device includes memory cells 1 and 2, each located in a point where a word line WL and a bit line BL cross each other, having each of NMOS transistors NM0 and NM1, and cell capacitors CO and C1, and a sense amplifier 3 connected to each pair of bit lines BL0,/BL0 and BL1,/BL1, thereby sensing a data.
Here, in the above memory cells 1 and 2, each gate and drain of the NMOS transistors NM0 and NM1 are connected to the word line WL and the bit line BL, respectively, and each electrode of the cell capacitors CO and Cl is connected to each source of the NMOS transistors NM0 and NM1, respectively, and the other electrode thereof is connected to an input terminal of a cell plate voltage Vcp.
The construction of the conventional memory cell will now be described in detail.
First, supposing that high and low level data are stored in the cell capacitors C0 and C1, respectively, and the data is continuously written by the refresh operation, here, the bit line pairs BL0,/BL0 and BL1,/BL1 are precharged at a Vdd/2 level and receive the cell plate voltage Vcp of the Vdd/2 level.
As shown in FIG. 2A, when the word line WL is enabled, and NMOS transistors NM0 and NM1 of the memory cells 1 and 2 are turned on, a voltage difference is each formed between the bit lines BL0 and /BL0, and the bit lines BL1 and /BL1 by charge sharing, and the voltage difference is amplified by the sense amplifier 3, thus the high and low level data become Vdd and Vss, respectively.
Accordingly, as shown in FIGS. 2B and 2C, the bit lines BL0 and BL1 become Vdd and Vss, respectively, by the sensing operation of the sense amplifier 3.
Here, since the NMOS transistors NM0 and NM1 of the memory cells 1 and 2 are being turned on, as shown in FIG. 2E and 2F, the electrodes d0 and d1 of the cell capacitors C0 and C1 also become Vdd and Vss, respectively.
Next, if the word line WL is disabled, the cell capacitors C0 and C1 become Vdd and Vss, respectively, and the high and low level data are again stored in the cell capacitors C0 and C1, respectively.
However, the data stored in each of the cell capacitors C0 and C1 is externally dissipated in leakage current. Thus, a DRAM generally performs the refresh operation of reading and again writing the data from the cell capacitors C0 and C1, before the data is completely dissipated.
Accordingly, since the data stored in the cell capacitors C0 and C1 are dissipated in leakage current, the construction of the conventional memory cell generally may have a short refresh interval, thereby increasing power consumption.